Dual channel, dual potential open-circuit test apparatus

ABSTRACT

A detector network for the indentification of discontinuities in integrated circuit lead connections in the presence of two different potentials such as positive or negative test pulses or different steady state voltages.

United States Patent Bobbitt [4 1 Feb. 12, 1974 3,617,879 11/1971Mugnier 32 4/l33 X Wehh. 324/5l X Davis 324/5l Primary Examiner-GerardR. Strecker Attorney, Agent, or Firm-James A. Pershon; Edward W Hughes[57] ABSTRACT A detector network for the indentiiication ofdiscontinuities in integrated circuit lead connections in the presenceof two different potentials such as positive or negative test pulses ordifferent steady state'voltages.

3 Claims, 3 Drawing Figures l l TO ERROR 52 58 LATCH 4 3 INDICATOR l NOFAULT CONDITION l 7 4 UNIT UNDER TEST TEST CIRCU|T- 28 & I325 7 0 1 l IRELAY I6 22 O +\2v 1 l J) 26 H3 7 AMPLIFIER I 60 BO +5v F3? 7 8 DIODEGATE +5v I OF A 1 Q c I5 I 1 9B l 36 6| l J J,

| RELAY 6 1 59 AMPLIFIER E moo: GATE PA-TENIH] FEB I 21974 sum 1 OF 3M50 w o 10:662. 10.53 mm mommw E ra EZZ IO PATENIEDFEB I 21914 SHEET 2(If 3 MEG N M365 O NOE l g Nv 5 F mm, EEJHEE 9m dzzfi 2 m mm T 7 29.528mommm mm MEG mm 305 w g K fizz/Io DUAL CHANNEL, DUAL POTENTIALOPEN-CIRCUIT TEST APPARATUS BACKGROUND OF THE INVENTION Plasticencapsulated integrated circuits are prone to intermittent open circuitconditions at bonding connections because the connecting leads arebonded or embedded in plastic which expands and contracts withtemperature changes. I

The present invention comprises a detector circuit which monitors theterminals of the integrated circuit in the presence of steady state orprobing positive and negative pulses, detects the lead discontinuitiesand generates a signal or sets an error latch circuit which identifiesthe open lead condition.

DESCRIPTION OF THE PRIOR ART Heretofore oscilloscopes have been utilizedto monitor circuit conditions of an encapsulated integrated circuit whenthe encapsulated device was heated by a hotplate positioned in a testbox and tested under one or more temperature conditions.

The oscilloscope method is slow and cumbersome, especially when appliedto the procedures employed in connection with equipment for inspecting alarge number of devices at many different temperature levels.

SUMMARY OF THE INVENTION Therefore, in accordance with the inventionclaimed, a new detector network is provided for detecting intermittentbond connections at integrated circuit terminals which may be pulsed athigh speeds and used in combination with other like circuits tointerrogate many circuits at one time. To accommodate the directionalcharacteristics of integrated circuit elements terminated at the bondedconnections, two different potentials such as, for example, positive andnegative potentials or probing pulses are employed in the testingprocedure.

It is, therefore, an object of this invention to provide an electronicdetections circuit to detect the presence of an open connection'in anintegrated circuit in the presence of a probing pulse.

Another object of this invention is to provide a detector circuitcapable of detecting a circuit dicontinuity in the presence of twodifferent potentials such as a positive or a negative probing pulse.

A further object of this invention is to provide a detection circuitwhich can function at a high repetition rate to permit rapid andrepeated test operations.

A still further object of this invention is to provide a detectioncircuit which may be readily activated under high speed operatingconditions to permit selection of a desired test terminal.

A still further object of this invention is to provide a detectioncircuit which has the capability of setting an error latch indicator toidentify the location of a detected open lead connection.

Further objects and advantages of the invention will become apparent asthe following description proceeds and the features of novelty whichcharacterize this in- .vention will be pointed out with particularity inthe claims annexed to and forming part of this specification.

BRIEF DESCTIPTION OF THE DRAWINGS The present invention may be morereadily described by reference to the accompanying drawings, in which:

FIG. I is a schematic drawing of the preferred embodiment of thedetector network.

FIG. 2 is a partial view of the schematic drawing of the preferredembodiment of the detector network shown in FIG. 1 with relays set toenable the upper channel of the detector. The network is shown with circled arrows representing signal levels in the presence of abnormalconditions at the unit under test.

FIG. 3 is a partial view of a schematic drawing of the preferredembodiment of the detector network shown in FIG. 1 with relays set toenable the lower channel of the detector network shown with circledarrows representing signal levels in the presence of abnormal conditionsat the unit under test.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring more particularly tothe drawing by characters of reference, FIG. 1 discloses the detectornetwork comprising an upper channel 1 and a lower channel 2, a channelselector switch 3, a switch 3a for controlling the potential at one endof the circuit being tested and an output gate 4.

Channel selector switch 3 and control switch 3a are three-positionsynchronized switches with positions A, B and an Off" position C. Whenswitch 3 is set in position A, channel is selected by connecting inputline 5 to ground. When set on position B, switch 3 selects channel 2 byconnecting input line 6 to ground. When switch 3 is set on the Off"position C, neither channel -1 nor channel 2 is selected.

Channel I is comprised of an enabling relay 7, a diode gate 8, a biasedamplifier 9, a comparator l0 and two NAND gates 11 and 12.

Relay 7 has a coil 13 anda contact mechanism 14 which is normally in theopen position when coil 13 is not energized. The upper end of coil 13 isconnected to a positive voltage source shown as +12V. Coil 13 isenergized by connecting its lower end to ground 15 through input line 5and switch 3. when switch 3 is set in position A. When. coil 13 is thusenergized its contacts 14 are closed, connecting input terminal 16 ofamplifier 9 to the unit under test.

Amplifier 9.includes resistors and 22, diode 23 and transistor 17. Whencontacts 14 of relay 7 are open, a current I flows from the +5V source24 through resistor 21 into base 20 of transistor 17. Current I, is ofsufficient amplitude to turn on transistor 17 or to set it in a nearsaturated condition, i.e., its anode-to-cathode voltage will be in theregion of one-half volt or less. The emitter 19 of transistor 17 andhence input terminal 25 of comparator 10 are approximately 4.5 voltsabove ground. When contacts 14 of relay 7 are closed, the condition oftransistor 17 is dependent upon the voltage present on line 28, which isconnected to the unit under test. A negative or low positive potentialon line 28 will tend to turn transistor 17 off so that the potential atits emitter 19 will also be at or near ground potential. If line 28 ispositive or if line 28 is terminated in a high impedance such as an opencircuit at the unit under test, transistor 17 will then be in the Oncondition as in the case when contacts 14 of relay 7 were open.Amplifier 9 thus delivers a high or a low potential to input terminal 25of comparator 10 depending upon the potential on input line 28. In orderfor a potential to exist on line 28 when continuity exists in the testcircuit under test, end 2811 of the test circuit is connected to groundwhen selector switch 3 is in position A. This is accomplished by thecontrol switch 3a which is synchronized with switch 3, as shown in FIG.1.

Comparator 10 is a type of integrated circuit which compares two inputpotentials and delivers at its output terminal a voltage levelindicating which of the two potentials is more positive. Comparator 10has two input terminals 25 and 26 which are connected to the twopotentials which are to be compared, and it has an output terminal 27.Input terminal 25 is known as a noninverting input terminal because aninput at this terminal which is more positive than the potential at theother input terminal will cause the output terminal 27 to be at arelatively high positive voltage with respect to ground. Input terminal26 is shown with a small bubble at its entrance and is known as aninverting input terminal because a signal at this input terminal whichis more positive than the signal at the other input terminal causes theoutput at terminal 27 to be at a relatively low positive potential or ata potential which is negative with respect to ground. The comparator isshown as typically represented and the discussion ofits operation asoutlined above is amplified by many texts and handbooks which arereadily available. Specifications for a typical comparator are given onpages 3-91 of The Integrated Circuits Catalog for Design Engineers,First Edition, published by Texas Instruments, Inc. See also OperationalAmplifier, RCA Integrated Circuit Fundamentals, Radio Corporation ofAmerica, 1966 (Chapter on Integrated-Circuit Operational-AmplifierConfiguration beginning on page 60).

Diode gate 8 includes a diode 29 and a resistor 30. The input terminal60 of diode gate 8 is at the cathode of diode 29; the output terminal ofthe gate is at the anode of diode 29. When input line 5 is groundedthrough position A of switch 3, the cathode of diode 29 is at groundpotential. Current flowing from the +5V source 8a through resistor 30and through diode 8 from anode to cathode raises the anode potential toapproximately 0.6 volts above ground. The output of the gate for thiscondition is thus approximately 0.6 volts as delivered to input terminal31 of NAND gate 11. When input line 5 is open, the cathode of diode 29is connected to a +12 volt potential through coil 13 of relay 7. Thecathode of diode 29 is thus more positive than the anode, and the diodeis said to be reverse biased. Under this condition, substantially nocurrent flows through the diode or through resistor 30 and the anode ofdiode 8 as well as the input terminal 31 of gate 11 are at or near the+5 volt potential.

NAND gates 11 and 12 are commoy used logic circuits having one or moreinput terminals and one output terminal. If any or all of the inputterminals of one of these gates are low (a volt or less positve withrespect to ground), the output terminal will be high (2 volts or morepositive with respect to ground). If all input terminals are high (2volts or higher), the output terminal will be low (less than 1 volt). ANAND gate in which only one input terminal is employed is called aninverter. In this case the output will be low when the input is high andthe output will be high when the input is low.

For description of NAND (or NOT AND) gates see Digital ComputerFundamentals, Thomas C. Bartee, McGraw Hill Book Co. I960, pp. 106-110or Com puter Basics, vol. 6, pp. 101-102, Bobbs Merrill Co., Inc. I962.

With the exception of amplifier 32, the major network elements ofchannel 2 are the same as those employed in channel 1. Amplifer 32 isthe same as amplifer 9 exceptthat amplifier 32 has no resistor connectedbetween collettor 33 and base 34 of its transistor 35. In this case,there is no source of base drive current when relay contact 36 of relay54 is open, and transistor 35 is thus turned off so that its emitter 37is near ground potential. The same contions are true when contact 36 isclosed and input line 28 terminates in a high impedance or connects to alow positive or to a negative voltage. A positive signal level on line28 with contact 36 closed supplies drive current into base 34, causingan amplifier current to flow from collector 33 to emitter 37 oftransistor 35. This positive signal level occurs by switch contact 3a inposition B connecting end of 8a of the test circuit to approximately a+1 volt source. This same amplified current flowing through resistor 38to ground terminal 15 produces a voltage drop across resistor 38 andsets a voltage level at emitter 37 that is within approximately 0.6volts as positive as the signal on line 28.

Channel 2 differs from channel 1 in a second respect: the output ofamplifier 9 of channel 1 is connected to the non-inverting inputterminal 25 of comparator 10, whereas the output of amplifier 32 ofchannel 2 is connected to the inverting input terminal 39 of comparator41.

Output gate 4 is identical to gates 12 and 42. Operation of the detectorcircuit and signal levels at points throughout the network are dependentupon the position of switch 3 and upon signals present on input line 28.

The following conditions exist when channel selector switch 3 is in theOff position: The input terminals of diode gate 8 of channel 1 and of anidentical diode gate 43 of channel 2 are both at a positive 12 volts.The output terminals 31 and 44 are thus at or near +volts. Outputterminals 46 and 47, respectively, of gates 11 and 45 are thus both low,as are the corresponding input terminals 48 and 49, respectively, ofgates 12 and 42. This condition is represented by the arrows pointingdownward at input terminals 48 and 49.

Because contact 14 of relay 7 is open when selector switch 3 is in theOff position, transistor 17 is On" and a positive level exists at inputterminal 25 of comparator 10. Because this positive level atnon-inverting input terminal -25 is more positive than the +3.8 voltspresent at inverting input terminal 26, the output termimi] 27 ofcomparator 10 is also high, as indicated by the arrow pointing upward onthe line connecting output terminal 27 of comparator 10 with inputterminal 50 of gate 12. Because one of the input terminals (terminal 48)of gate 12 is low, the output terminal 51 of gate 12 is high, asindicated by the arrow pointing upward on the line connecting outputterminal 51 of gate 12 to input terminal 52 of gate 4.

Contact 36 of relay 54 is also open when selector switch 3 is in the Offposition. Transistor 35 of amplifier 32 is thus in the Off conditionanthe input terminal 39 of comparator 41 is thus substantially at 0volts. Because the voltage at inverting input terminal 39 of comparator41 is lower than the positive 0.1 volt reference connected tonon-inverting input terminal 40, the output of comparator 41 at terminal55 is high, as indicated by te arrow pointing upward on the lineconnecting output terminal 55 of comparator 41 to input temminal 56 ofgate 42. Because input terminal 49 of gate 42 is low, the outputterminal 57 of, gate 42 is high, as indicated by the arrow pointingupward on the line connecting output terminal 57 of gate 42 to inputterminal 53 of gate 4.

Because both input terminals 52 and 53 of gate 4 are high, outputterminal 58 of gate 4 is low, as indicated by the arrow pointingdownward. A low level on line 58 leading to the error latch andindicator is a no fault condition and will not set the error latch.

FIG. 2 shows signal levels existing with selector switch 3 set inposition .A to enable channel 1. When selector switch 3 is in positionA, coil 59 of relay 54 is not energized and signal levels for channel 2are the same as described above for selector switch 3 in the Off"position. The signal at input 53 of gate 4 is thus high, as indicated bythe arrow pointing upward on the line leading to terminal 53.

When switch 3 is moved from the Off position to position A, the signallevel at the input of diode gate 8 switches from a high level (+12volts) to a low level (ground). A corresponding reversal (from low tohigh) occurs in the signal level at input terminal 48 of gate 12 asindicated by the arrow pointing upward.

For the opencondition of contacts 14 of relay 7 the signal level atinput terminal 16 of amplifier 9 was high. For the closed condition ofcontacts 14 as shown in FIG. 2 and with continuity to ground or to anegative potential through a normal lead connection in the unit undertest, the signal level at input terminal 16 reverses to a low level. Acorresponding reversal of the signal at input terminal 50 of gate 12results as indicated by the arrow pointing downward. Signal levels atoutputs of gates 12,- 42 and 4 for these conditionsare indicated by lthe remaining arrows and may be derived on the basis of earlierexplanations of gate operating characteristics. Again, the arrowpointing downward at output terminal 58 indicates NO FAULT in the unitunder test.

In FIG. 2, which represents the same circuit shown in FIG. 1 withdetails removed for the sake of clarity, some of the arrows pointingupward or downward are different than in FIG. 1. The circled arrowsindicate signal levels in that part of channel 1 which are affected byconditions in the unit under test. More specifically, the circled arrowsin FIG. Z'indicate signal levels corresponding to fault conditions inthe unit under test.

If conditions in the unit under test are'not normal, i.e., if the leadconnection at the selected terminal of the unit under test is open, thesignal level at input terminal 16 of amplifier 9 will be high.

FIG. 3 shows signal levels present throughout the detector network whenselector switch 3 is set in position B, which energizes relayv54,closing contacts 36 as shown; The arrows pointing upward and downwardagain represent high and low signal levels prevailing in the case ofnormal or abnormal conditions at the unit under test. Circled arrowsindicate a fault or opencircuit condition at the unit under test.

. On the basis of the foregoing explanations of circuit operation, it isseen that a negative signal at input terminal 16 of amplifier 9 ofchannel 1 corresponds to a normal condition at the unit under test,whereas a positive signal at input terminal 61 of amplifier 32 ofchannel 2 corresponds to a normal condition at the unit under test. Itis this feature which enables the detector network to detect faults witheither positive or negative probing pulses or two different potentialsof like or different polarities. Selection of .the appropriate channelis accomplished by switch 3 when it is set in position A or position B.I

Although but one embodiment of the invention has been illustrated anddescribed, it will be obvious to one skilled in the art that variouschanges and modifications may be made without departing from the spiritof the invention and scope of the appended claims.

What is claimed is: g

1. A systm for converting information received from a circuit under testenergized by two different voltage potentials into indicator signals,said system comprising:

a pair of test channels,

a channel selector switch,

an output gate,

said selector switch being arranged to selectively connect a circuitunder test between either of the two different potentials and either ofsaid channels,

said first channel comprising. a first amplifier, having an inputterminal connected to the circuit under test with one potential appliedthereto by said selector switch and an output terminal connected to oneterminal of a first comparator, a second gate having a first inputterminal connected to an output terminal of said comparator, a firstdiode gate' rendered conductive when said selector switch connects saidfirst channel to the circuit under test and having an output terminalconnected to a second input terminal of said second gate to permitconduction of said second gate according to the first input terminal ofsaid second gate, said second gate having an output terminal connectedto a first terminal of said output gate, said first comparator having asecond input terminal connected to a source of potential which controlsthe polarity of the output signal of said first comparator,

said second channel comprising a second amplifier having an inputterminal connected tothe circuit under test with the second potentialapplied thereto by said selector switch and an output terminal connectedto one terminal of a second comparator, a third gate having a firstinput terminal con nected to an output terminal of said secondcomparator, a second diod gate rendered conductive when said selectorswitch connects said second channel to the circuit udder test and havingan output terminal connected to a second input terminal of said thirdgate to permit conduction of said third gate according to the firstinput terminal of said third gate, said third gate having an outputterminal connected to a second terminal of said output gate, said secondcomparator having a secondinput terminal connected to a source ofpotential which controls the polarity of the output signal of saidsecond comparator,

said first channel transmitting a given signal to the first inputterminal of said output gate when said selector switch connects thecircuit under test to said first channel and continuity exists in thecircuit under test,

said second channel transmitting a given signal to the second inputterminal of said output gate when said selector switch connects thecircuit under test to said second channel and continuity exists in thecircuit under test,

said first diode gate rendered nonconductive when the circuit under testis connected via said selector switch to said second channel,

said second diode gate rendered nonconductivc,

when the circuit under test is connected via said selector switch tosaid first channel,

said output gate transmitting an error signal when continuity does notexist in the circuit under test.

under test to a different potential.

1. A systm for converting information received from a circuit under testenergized by two different voltage potentials into indicator signals,said system comprising: a pair of test channels, a channel selectorswitch, an output gate, said selector switch being arranged toselectively connect a circuit under test between either of the twodifferent potentials and either of said channels, said first channelcomprising a first amplifier, having an input terminal connected to thecircuit under test with one potential applied thereto by said selectorswitch and an output terminal connected to one terminal of a firstcomparator, a second gate having a first input terminal connected to anoutput terminal of said comparator, a first diode gate renderedconductive when said selector switch connects said first channel to thecircuit under test and having an output terminal connected to a secondinput terminal of said second gate to permit conduction of said secondgate according to the first input terminal of said second gate, saidsecond gate having an output terminal connected to a first terminal ofsaid output gate, said first comparator having a second input terminalconnected to a source of potential which controls the polarity of theoutput signal of said first comparator, said second channel comprising asecond amplifier having an input terminal connected to the circuit undertest with the second potential applied thereto by said selector switchand an output terminal connected to one terminal of a second comparator,a third gate having a first input terminal connected to an outputterminal of said second comparator, a second diod gate renderedconductive when said selector switch connects said second channel to thecircuit udder test and having an output terminal connected to a secondinput terminal of said third gate to permit conduction of said thirdgate according to the first input terminal of said third gate, saidthird gate having an output terminal connected to a second terminal ofsaid output gate, said second comparator having a second input terminalconnected to a source of potential which controls the polarity of theoutput signal of said second comparator, said first channel transmittinga given signal to the first input terminal of said output gate when saidselector switch connects the circuit under test to said first channeland continuity exists in the circuit under test, said second channeltransmitting a given signal to the second input terminal of said outputgate when said selector switch connects the circuit under test to saidsecond channel and continuity exists in the circuit under test, saidfirst diode gate rendered nonconductive when the circuit under test isconnected via said selector switch to said second channel, said seconddiode gate rendered nonconductive when the circuit under test isconnected via said selector switch to said first channel, said outputgate transmitting an error signal when continuity does not exist in thecircuit under test.
 2. The system set forth in claim 1 wherein: saidselector switch is provided with an OFF position and when said selectorswitch is in said OFF position said first and second channels eachtransmit to said output gate signals indicative of an unenergizedcondition, said output gate transmitting an output signal indicative ofa fault condition.
 3. The system set forth in claim 1 wherein: saidselector switch simultaneously connects one end of the circuit undertest to either of said first and second potentials and the other end ofthe circuit under test to a different potential.